Description has been made above regarding the present disclosure with reference to the embodiments. The above-described embodiments have been described for exemplary purposes only, and are by no means intended to be interpreted restrictively. Rather, it can be readily conceived by those skilled in this art that various modifications may be made by making various combinations of the aforementioned components or processes, which are also encompassed in the technical scope of the present disclosure. Description will be made below regarding such modifications.

Description has been made assuming that the first circuit block BLK1 and the second circuit block BLK2 are configured as a single core. However, the present invention is not restricted to such an arrangement.

For example, the first output stage including the first high-side transistor and the first low-side transistor of the first circuit block and the second output stage including the second high-side transistor and the second low-side transistor of the second circuit block may be designed as a single core. In this case, the two output stages may preferably be laid out on a semiconductor chip such that they are mirror images of each other.

Alternatively, a portion including the first output stage and the first pre-driver and a portion including the second output stage and the second pre-driver may be designed as a single core. In this case, the two portions may be laid out on a semiconductor chip such that they are mirror images of each other.

Also, there may be a difference in the size of the power transistor MH (ML) that corresponds to the output stage between the two circuit blocks BLK1 and BLK2.