FIG. 4A shows the multiplier circuits 30_0 to 30_7 as the multiplier circuit 30 and analog potential holding circuits 45_0 to 45_15 as the analog potential holding circuit 45 in addition to the control circuit 35 and the digital-analog converter circuit 36 illustrated in FIG. 2, FIG. 3A, and FIG. 3B. In the analog potential holding circuits 45_0 to 45_15, for example, the analog potential holding circuits 45_0 and 45_1 correspond to the analog potential holding circuits 45N and 45P illustrated in FIG. 3A and FIG. 3B. In FIG. 4A, a signal WW[0] to a signal WW[15] and signals CTR[0] to CTR[15] are shown as the signal WW and the signal CTR illustrated above in FIG. 2, FIG. 3A, and FIG. 3B, and a signal DATA is shown as digital data output from the control circuit 35 to the digital-analog converter circuit 36. A pair of signals in the signal WW[0] to the signal WW[15] correspond to the signal WWP and the signal WWN illustrated in FIG. 3A and FIG. 3B. A pair of signals in the signals CTR[0] to CTR[15] correspond to the signal CTRN and the signal CTRP illustrated in FIG. 3A and FIG. 3B.
