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Apparatus, memory device and method for storing parameter codes for asymmetric on-die-termination

專(zhuān)利號(hào)
US11888476B2
公開(kāi)日期
2024-01-30
申請(qǐng)人
SAMSUNG ELECTRONICS CO., LTD.（KR Suwon-si）
發(fā)明人
Daehyun Kwon; Hyejung Kwon; Hyeran Kim; Chisung Oh
IPC分類(lèi)
H03K19/017; H03K19/00; H03K19/17736; H03K19/17772
技術(shù)領(lǐng)域
odt,pull,circuit,signal,device,may,dq,second,line,data
地域： Suwon-si

摘要

An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

說(shuō)明書(shū)

When the receiver 622 of the second device 120 receives a signal through the signal line 130, each of the NMOS transistors ON1 to ONn of the second ODT circuit 124b may be turned on or off according to a second ODT control signal C2b[n:1] of n bits corresponding thereto. A termination resistance value according to the on/off state of the NMOS transistors ON1 to ONn may be provided through the signal line 130.

When no signal is transmitted through the signal line 130, all of the NMOS transistors ON1 to ONn of the second ODT circuit 124b may be turned off according to the second ODT control signal C2b[n:1] of n bits, and the second ODT circuit 124b may be disabled. Also, all of the NMOS transistors N1 to Nn of the pull-down circuit 612U operating as the ODT circuit 114b of the first device 110 may also be turned off according to the first ODT control signal C1b[n:1] of n bits, and the ODT circuit 114b may be disabled. During the non-transmission, the ODT circuits 114b and 124b of the first and second devices 110 and 120 are disabled, and thus, the signal line 130 may maintain a high-impedance state.

FIG. 8 is a diagram conceptually illustrating ODT circuits 114c and 124c of FIG. 1, and FIGS. 9A and 9B are circuit diagrams illustrating the ODT circuits 114c and 124c of FIG. 8.

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