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Apparatus, memory device and method for storing parameter codes for asymmetric on-die-termination

專利號
US11888476B2
公開日期
2024-01-30
申請人
SAMSUNG ELECTRONICS CO., LTD.(KR Suwon-si)
發(fā)明人
Daehyun Kwon; Hyejung Kwon; Hyeran Kim; Chisung Oh
IPC分類
H03K19/017; H03K19/00; H03K19/17736; H03K19/17772
技術領域
odt,pull,circuit,signal,device,may,dq,second,line,data
地域: Suwon-si

摘要

An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

說明書

According to an aspect of an example embodiment, an apparatus that is connected to an external device via a signal line, includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

According to an aspect of an example embodiment, an apparatus includes a plurality of signal pins, wherein the apparatus is connected to an external device through a signal line connected to a signal pin among the plurality of signal pins; an on-die termination (ODT) circuit connected to the signal line, the ODT circuit being set to a first ODT state; a mode register configured to store a first parameter code corresponding to a first operating condition of the ODT circuit and a second parameter code corresponding to a second operating condition of the ODT circuit; and a control circuit configured to set the ODT circuit to the first operating condition using the first parameter code in a symmetric ODT where a second ODT state of the external device corresponds to the first ODT state, and set the ODT circuit to the second operating condition using the second parameter code in an asymmetric ODT where the second ODT state of the external device is different from the first ODT state.

權利要求

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