The transmitter 824 of the second device 120 may include a pull-up circuit 824U and a pull-down circuit 824D coupled to the data line 830 and the second pin 820. The pull-up circuit 824U may include a plurality of PMOS transistors UP1 to UPn connected to the power voltage VDDQ line and the data line 830, and arranged in parallel. Each of the PMOS transistors UP1 to UPn may be turned on or off according to a second pull-up drive code PU2[n:1] corresponding thereto. The PMOS transistors UP1 to UPn corresponding to a bit value “0” of the second pull-up drive code PU2[n:1] are turned on so that the data line 830 may be driven at a logic high level. As additional transistors of the PMOS transistors UP1 to UPn are turned on, the driving capability of the pull-up circuit 824U may be increased.

The pull-down circuit 824D may include a plurality of NMOS transistors DN1 to DNn connected between the data line 830 and the ground voltage VSSQ line, and arranged in parallel. Each of the NMOS transistors DN1 to DNn may be turned on or off according to a second pull-down drive code PD2[n:1] corresponding thereto. The NMOS transistors DN1 to DNn corresponding to a bit value “1” of the second pull-down drive code PD2 [n:1] are turned on so that the data line 830 may be driven at a logic low level. As additional transistors of the NMOS transistors DN1 to DNn are turned on, the driving capability of the pull-down circuit 824D may be increased.