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Apparatus, memory device and method for storing parameter codes for asymmetric on-die-termination

專(zhuān)利號(hào)
US11888476B2
公開(kāi)日期
2024-01-30
申請(qǐng)人
SAMSUNG ELECTRONICS CO., LTD.（KR Suwon-si）
發(fā)明人
Daehyun Kwon; Hyejung Kwon; Hyeran Kim; Chisung Oh
IPC分類(lèi)
H03K19/017; H03K19/00; H03K19/17736; H03K19/17772
技術(shù)領(lǐng)域
odt,pull,circuit,signal,may,device,dq,second,line,data
地域： Suwon-si

摘要

An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

說(shuō)明書(shū)

When the data signal DQ is not transmitted through the data line 830, all of the PMOS transistors P1 to Pn of the pull-up circuit 814U operating as the ODT circuit 114c of the first device 110 may be turned off according to the first ODT control signal C1c[n:1] of n bits, and the first ODT circuit 114c may be disabled. All of the NMOS transistors UN1 to UNn of the pull-up circuit 824U operating as the ODT circuit 124c of the second device 120 may be also turned off according to the second ODT control signal C2c[n:1] of n bits, and the ODT circuit 124c may be disabled. Accordingly, during the data non-transmission, the ODT circuits 114c and 124c of the first and second devices 110 and 120 are disabled, and thus, the data line 830 may maintain a high-impedance state.

FIGS. 10 and 11 are diagrams illustrating an operation of the second device 120 associated with the ODT circuits 114c and 124c of FIG. 8. FIG. 10 illustrates a read operation on the second device 120, and FIG. 11 illustrates a write operation on the second device 120. It should be noted that the horizontal axis and the vertical axis in the timing diagrams illustrated in FIGS. 10 and 11, respectively, represent time and voltage levels, and are not necessarily shown in a constant ratio.

權(quán)利要求

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