Referring to FIGS. 1, 8, and 10, at a time T1, the first device 110 may issue a read command RD for a read operation on the second device 120 and provide the read command RD to the second device 120 through the signal line 130 (FIG. 1). The second device 120 may receive the read command RD, and the control circuit 122 may generate control signals for performing various memory operations in the second device 120 according to the read command RD. At this time, the ODT circuits 114c and 124c of the first and second devices 110 and 120 are in a disabled state. Accordingly, the first pin 810 of the first device 110 and the second pin 820 of the second device 120 may be set to a high-impedance state Hi-Z. Before the data signal DQ according to the read command RD is transmitted to the data line 830, the data line 830 between the first pin 810 and the second pin 820 may be maintained in the high-impedance state Hi-Z.

At a time T2, the first device 110 may enable the ODT circuit 114c to receive the data signal DQ according to the read command RD from the second device 120. Accordingly, the first pin 810 of the first device 110 may be changed from the high-impedance state Hi-Z to, for example, the power voltage VDDQ level, and the ODT circuit 114c may provide a termination resistance.

From a time T3 to a time T4, before outputting the data signal DQ according to the read command RD to the second pin 820, the second device 120 may pre-drive the data signal DQ, for example, having a logic low level during a period corresponding to a read preamble length.