Apparatus, memory device and method for storing parameter codes for asymmetric on-die-termination
摘要
說明書
At a time Tc, the first device 110 may transmit the data signal DQ according to the write command WR to the first pin 810 and the data line 830. At a time Td, the second device 120 may receive the data signal DQ of the first device 110 transmitted through the data line 830 via the second pin 820.
At a time Te, the first device 110 may complete transmission of the data signal DQ according to the write command WR. The first pin 810 may be changed to the high-impedance state Hi-Z by disabling the ODT circuit 114c of the first device 110.
At a time Tf, the second device 120 may complete reception of the data signal DQ according to the write command WR from the first device 110 and may disable the ODT circuit 124c. The second pin 820 of the second device 120 may be changed to the high-impedance state Hi-Z. When transmission of the data signal DQ according to the write command WR is completed, the data line 830 between the first pin 810 and the second pin 820 may maintain the high-impedance state Hi-Z.
