Apparatus, memory device and method for storing parameter codes for asymmetric on-die-termination
摘要
說明書
The second device 120 may be implemented as a volatile memory device. The volatile memory device may be implemented as random access memory (RAM), dynamic RAM (DRAM), or static RAM (SRAM), but is not limited thereto. For example, the second device 120 may include double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate (LPDDR), SDRAM, graphics double data rate (GDDR), SDRAM, Rambus dynamic random access memory (RDRAM), etc. Alternatively, the second device 120 may be implemented as a high bandwidth memory (HBM).
The second device 120 may be implemented as a nonvolatile memory device. For example, the second device 120 may be implemented as a resistive memory such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), etc.
A signal may be transmitted between the first device 110 and the second device 120 through a signal line 130. For the sake of brevity of the drawing, although it is illustrated that the signal is transmitted through one signal line between the first device 110 and the second device 120, the signal may be actually transmitted through a plurality of signal lines or a bus. The signal line(s) 130 between the first device 110 and the second device 120 may be connected through connectors. The connectors may be implemented as pins, balls, signal lines, or other hardware components.
