The signal transmitted through the signal line 130 may include, for example, a clock signal CK, a command signal CMD, and/or an address signal ADDR, and may be transmitted through the plurality of signal line(s) 130. The command signal CMD and the address signal ADDR may be referred to as a command/address CA signal. The second device 120 may receive the clock signal CK, the command signal CMD, and/or the address signal ADDR from the first device 110, and generate an internal signal corresponding to a function of the received clock signal CK, command signal CMD, and/or address signal ADDR. The second device 120 may perform a memory operation such as selecting a row and a column corresponding to a memory cell, writing data into the memory cell, or reading the written data according to the internal signal. Write data and read data transmitted/received between the first device 110 and the second device 120 will be described as a data signal DQ in FIG. 8.

The first device 110 may control the second device 120 to read data stored in the second device 120 or write data to the second device 120 in response to a write/read request from the host HOST. The first device 110 may provide the second device 120 with the clock signal CK, the command signal CMD, and/or the address signal ADDR, thereby controlling data write and/or read operations on the second device 120. As the second device 120 receives write data using the clock signal CK from the first device 110, the clock signal CK may be referred to as a write clock signal.