Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
地域：
CA
CA San Francisco
摘要
A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.
說明書
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This application is a continuation of U.S. patent application Ser. No. 17/449,748 titled “NON-LINEAR POLAR MATERIAL BASED Low POWER MULTIPLIER WITH TRANSMISSION-GATE BASED RESET MECHANISM,” filed Oct. 1, 2021, which is incorporated by reference in its entirety.
Typical multiplier cell includes a 1-bit full adder and an AND gate. The 1-bit full adder receives three or more inputs and may consist of several logic gates such as AND gate, OR, gate, XOR gates, inverters, and buffers. In complementary metal oxide semiconductor (CMOS) logic, a 2-input AND gate derived from a 2-input NAND gate and an inverter consists of six transistors. A 2-input OR gate derived from a 2-input NOR gate and an inverter consists of six transistors. A 2-input XOR gate may consist of at least six transistors. As the number of transistors increases, power consumption and area also increase. As devices are pushing down the power envelope to save battery power, existing circuit architecture for a multiplier cell presents challenges to the goal of lower power consumption.
The background description provided here is for the purpose of generally presenting the context of the disclosure. Unless otherwise indicated here, the material described in this section is not prior art to the claims in this application and are not admitted being prior art by inclusion in this section.
權利要求
We claim:1. An apparatus comprising:a 1-bit full adder comprising a majority gate or a minority gate, wherein the 1-bit full adder comprises non-linear polar material; and a reset mechanism comprising logic to condition first terminals of capacitors of the 1-bit full adder, the capacitors comprising the non-linear polar material, wherein the reset mechanism is to reset second terminals of the capacitors during a reset phase separate from an evaluation phase, and wherein the logic comprises one or more NAND gate and NOR gates. 2. The apparatus of claim 1 comprising: an AND gate which includes a majority gate or a minority gate having non-linear polar material, wherein the AND gate is coupled to the 1-bit full adder. 3. The apparatus of claim 2 , wherein the logic comprises:an inverter which is coupled to the AND gate; and a NAND gate coupled to an output of the inverter, wherein an output of the NAND gate is coupled a 3-input majority gate of the 1-bit full adder, and wherein the NAND gate is to receive a first reset to condition the output of the NAND gate during the reset phase. 4. The apparatus of claim 3 , wherein the inverter is a first inverter, wherein the logic comprises:a first NOR gate coupled to an output of the inverter, wherein the first NOR gate receives a second reset, wherein the second reset is inverse of the first reset, wherein an output of the first NOR gate is coupled to a 5-input majority gate of the 1-bit full adder, and wherein the second reset is to condition the output of the first NOR gate during the reset phase; a second inverter which is coupled to the 3-input majority gate; and a second NOR gate coupled to an output of the second inverter, wherein the second NOR gate is controllable by the second reset, wherein an output of the second NOR gate is a carry output, and wherein the second reset is to condition the output of the second NOR gate during the reset phase. 5. The apparatus of claim 4 comprises a third inverter coupled to the output of the second NOR gate, wherein an output of the third inverter is coupled to the 5-input majority gate. 6. The apparatus of claim 5 , wherein the logic comprises:a fourth inverter coupled to the 5-input majority gate; and a third NOR gate coupled to an output of the fourth inverter, wherein the third NOR gate is controllable by the second reset, wherein the second reset is to condition the output of the third NOR gate during the reset phase, and wherein the output of the third NOR gate is a sum output. 7. The apparatus of claim 6 , wherein the reset mechanism comprises:a first pull-up device coupled to the AND gate such that the first pull-up device is connected to the second terminals of a first set of capacitors of the AND gate, wherein the first pull-up device is controllable by a first control; and a first pull-down device controllable by a second control, wherein the first pull-down device is coupled to the second terminals of the first set of capacitors of the AND gate. 8. The apparatus of claim 7 , wherein the reset mechanism includes:a second pull-up device which is controllable by a third control, wherein the second pull-up device is coupled to the second terminals of a second set of capacitors of the 1-bit full adder; and a second pull-down device which is controllable by a fourth control, wherein the second pull-down device is coupled to the second terminals of the second set of capacitors of the 1-bit full adder. 9. The apparatus of claim 8 , wherein the apparatus comprises:a third pull-up device which is controllable by a fifth control, wherein the third pull-up device is coupled to the second terminals of a third set of capacitors of the 1-bit full adder; and a second pull-down device which is controllable by a sixth control, wherein the second pull-down device is coupled the second terminals of the third set of capacitors of the 1-bit full adder. 10. The apparatus of claim 1 , wherein the non-linear polar material includes ferroelectric material, wherein the ferroelectric material includes one of:Bismuth ferrite (BFO) with a first doping material wherein the first doping material is one of Lanthanum or elements from lanthanide series of periodic table; Lead zirconium titanate (PZT) or PZT with a second doping material, wherein the second doping material is one of La or Nb; a relaxor ferroelectric which includes one of: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), Barium Titanium-Bismuth Zinc Niobium Tantalum (BT-BZNT), or Barium Titanium-Barium Strontium Titanium (BT-BST); a perovskite which includes one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3; a first hexagonal ferroelectric which includes one of: YMnO3 or LuFeO3; a second hexagonal ferroelectric of a type h-RMnO3, where R is a rare earth element which includes one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); Hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides; Hafnium oxides as Hf1-x Ex Oy, where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, wherein x and y are first and second fractions, respectively; Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N or Al(1-x-y)Mg(x)Nb(y)N, where x and y and third and fourth fractions, respectively; y doped HfO2, where y includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y; Niobate type compounds LiNbO3, LiTaO3, Lithium iron Tantalum Oxy Fluoride, Barium Strontium Niobate, Sodium Barium Niobate, or Potassium strontium niobate; or an improper ferroelectric which includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 to 100. 11. An apparatus comprising:an AND gate comprising a majority gate or a minority gate having non-linear polar material, wherein the AND gate is to receive a multiplier and a multiplicand; a 1-bit full adder comprising a majority gate or a minority gate coupled to the AND gate, wherein the 1-bit full adder comprises non-linear polar material, and wherein the 1-bit full adder is to receive a sum input and a carry input; and a reset mechanism comprising logic to condition first terminals of capacitors of the AND gate and the 1-bit full adder, the capacitors comprising the non-linear polar material, wherein the reset mechanism is to reset second terminals of the capacitors during a reset phase separate from an evaluation phase, and wherein the reset mechanism is to apply a predetermined input to the multiplier, the multiplicand, the sum input, and the carry input during the reset phase. 12. The apparatus of claim 11 , wherein the reset mechanism is to sequentially pull-up and pull-down the second terminals during the reset phase, and to allow the second terminals to float during the evaluation phase. 13. The apparatus of claim 11 , wherein the logic includes at least one NOR gate and a NAND gate to condition the first terminals of the capacitors. 14. The apparatus of claim 11 , wherein the non-linear polar material comprises ferroelectric material. 15. The apparatus of claim 11 , wherein the reset mechanism is to reset the second terminals of the capacitors substantially simultaneously. 16. A system comprising:a processor circuitry to execute one or more instructions; a communication interface communicatively coupled to the processor circuitry; and a memory coupled to the processor circuitry, wherein the processor circuitry comprises a multiplier circuitry which includes:a majority gate or a minority gate having non-linear polar material, wherein the majority gate or the minority gate is coupled to a NOR gate or a NAND gate; and a reset mechanism to a reset a set of nodes coupled to the non-linear polar material during a reset phase separate from an evaluation phase, wherein a node from the set of nodes is coupled to the NOR gate or the NAND gate, and wherein the NOR gate or the NAND gate is controllable by the reset mechanism. 17. The system of claim 16 , wherein the set of nodes includes a first node, wherein the reset mechanism comprises:a pull-down device coupled to the majority gate or the minority gate such that the pull-down device is connected to the first node which connects to the non-linear polar material, wherein the pull-down device is controllable by a first control; and a pull-up device coupled to the majority gate or the minority gate such that the pull-up device is connected to the first node connecting the non-linear polar material, wherein the pull-up device is controllable by a second control. 18. The system of claim 17 , wherein the reset mechanism is to condition inputs to the majority gate or the minority gate, and to sequentially pull-up and pull-down the pull-up device and the pull-down device, respectively, during the reset phase. 19. The system of claim 17 , wherein the reset mechanism is to sequence a pull-up event and a pull-down event according to logic condition of inputs to the majority gate or the minority gate. 20. The system of claim 17 , wherein the non-linear polar material includes one of a ferroelectric material or paraelectric material.
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