Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
In various embodiments, the multiplier cell comprises majority and/or minority gates. Each of these gates includes a floating node (also referred to as the summing node). The floating node connects to the capacitors of the majority and/or minority gates, wherein the capacitors comprise non-linear polar material. A particular charge balance may be needed to be maintained at the floating node to get the majority (or minority) function. However, over time, the charge on the floating node leaks away due to the leakage of the various components present in a system comprising the multiplier cell. Source of this leakage can be leakage from a gate of a transistor coupled to the floating node. The source of the leakage can also be from the capacitors themselves and any other components coupled to the floating node. In some embodiments, a reset mechanism is provided which reestablishes the charge balance on the floating node for correct functionality. In some embodiments, the reset mechanism is enabled after a predetermined or programmable period. For example, the reset mechanism is enabled every 1 to 2 microseconds.
