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Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism

專(zhuān)利號(hào)
US11888479B1
公開(kāi)日期
2024-01-30
申請(qǐng)人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Amrita Mathuriya; Rafael Rios; Ikenna Odinaka; Rajeev Kumar Dokania; Sasikanth Manipatruni
IPC分類(lèi)
H03K19/23; H03K19/0185; G06F7/487; H03K19/017; G06F7/501; H03K19/17736
技術(shù)領(lǐng)域
reset,gate,majority,pull,capacitors,adder,minority,multiplier,gates,node
地域： CA CA San Francisco

摘要

A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

說(shuō)明書(shū)

Example 5: The apparatus of example 4, wherein the nodes include a first node, wherein the reset mechanism comprises: a first pull-down device coupled to the AND gate such that the first pull-down device is connected to the first node which connects to the non-linear polar material, wherein the first pull-down device is controllable by a first control; and a first pull-up device coupled to the AND gate such that the first pull-up device is connected to the first node connecting the non-linear polar material, wherein the first pull-up device is controllable by a second control.

Example 6: The apparatus of example 5, wherein the reset mechanism includes: a first transmission gate which is controllable by a third control and a fourth control, wherein the first transmission gate is coupled to an output of the AND gate and an input of a 5-input majority gate of the 1-bit full adder; and a second pull-down device which is controllable by the third control, wherein the second pull-down device is coupled to the first transmission gate and the input of the 5-input majority gate of the 1-bit full adder.

Example 7: The apparatus of example 6, wherein the reset mechanism includes: a second transmission gate which is controllable by the third control and the fourth control, wherein the second transmission gate is coupled to the output of the AND gate and an input of a 3-input majority gate of the 1-bit full adder; and a second pull-up device which is controllable by the third control, wherein the second pull-up device is coupled to the second transmission gate and the input of a 3-input majority gate of the 1-bit full adder.

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