Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
Example 11: The apparatus of example 10, comprises a buffer coupled to the third node, wherein the reset mechanism includes: a fourth transmission gate controllable by the third control and the fourth control, wherein the fourth transmission gate is coupled to an output of the buffer and a sum output; and a sixth pull-down device controllable by the third control, wherein the sixth pull-down device is coupled to the fourth transmission gate and sum output.
Example 12: The apparatus of example 4, wherein the reset nodes include a first node, wherein the AND gate is to receive a multiplier and a multiplicand, wherein the AND gate comprises: a first capacitor to receive the multiplier, the first capacitor coupled to the first node; a second capacitor to receive the multiplicand, the second capacitor coupled to the first node; a third capacitor coupled to a ground node, wherein the third capacitor is coupled to the first node, wherein the first capacitor, the second capacitor, and the third capacitor include non-linear polar material; and a driver circuitry having a capacitive input coupled to the first node, and an output which is to provide a majority logic function of the multiplier, the multiplicand, and a voltage on the ground node.
Example 13: The apparatus of example 1, comprising an AND gate coupled to the 1-bit full adder, wherein the AND gate includes a CMOS AND gate.
