Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
In some embodiments, when the non-linear polar material is a ferroelectric material, the inputs are set such that one of the multiplier and multiplicand inputs is set to logic 0 while the other is set to logic 1. The carry input and sum input are also set to 0. The reset mechanism then sets voltages on the floating nodes of the multiplier cell during a reset phase. Once the reset phase expires, the normal phase (or evaluation phase) begins. During the evaluation phase, the reset mechanism is disabled. The reset mechanism includes pull-up and pull-down devices coupled to the floating nodes. In some embodiments, when the non-linear polar material is a ferroelectric material, the three capacitors of the 3-input majority gates are input 0, 0, and 1, respectively. In that case, the reset mechanism first pulls up the floating nodes and then pulls down the floating nodes, in accordance with some embodiments. In some embodiments, when the non-linear polar material is a ferroelectric material, the five capacitors of the 5-input majority gates are input 0, 0, 0, 1, and 1 respectively. These inputs can be forced by the reset mechanism or provided from external source (e.g., by setting the voltages of sum input and carry input) and/or using transistors to force a value. Under these conditions for the input voltages of the non-linear capacitors, the reset mechanism first pulls up the floating nodes and then pulls down the floating nodes, in accordance with some embodiments.
