Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
Example 3a: The apparatus of example 2a, wherein the logic comprises: an inverter which is coupled to the AND gate; and a NAND gate coupled to an output of the inverter, wherein an output of the NAND gate is coupled a 3-input majority gate of the 1-bit full adder, wherein the NAND gate is to receive a first reset to condition the output of the NAND gate during the reset phase.
Example 4a: The apparatus of example 3a, wherein the inverter is a first inverter, wherein the logic comprises: a first NOR gate coupled to an output of the inverter, wherein the first NOR gate receives a second reset, wherein the second reset is inverse of the first reset, wherein an output of the first NOR gate is coupled to a 5-input majority gate of the 1-bit full adder, wherein the second reset is to condition the output of the first NOR gate during the reset phase; a second inverter which is coupled to the 3-input majority gate; and a second NOR gate coupled to an output of the second inverter, wherein the second NOR gate is controllable by the second reset, wherein an output of the second NOR gate is a carry output, wherein the second reset is to condition the output of the second NOR gate during the reset phase.
Example 5a: The apparatus of example 4a comprises a third inverter coupled to the output of the second NOR gate, wherein an output of the third inverter is coupled to the 5-input majority gate.
Example 6a: The apparatus of example 5a, wherein the logic comprises: a fourth inverter coupled to the 5-input majority gate; and a third NOR gate coupled to an output of the fourth inverter, wherein the third NOR gate is controllable by the second reset, wherein the second reset is to condition the output of the third NOR gate during the reset phase, wherein the output of the third NOR gate is a sum output.
