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Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism

專利號
US11888479B1
公開日期
2024-01-30
申請人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Amrita Mathuriya; Rafael Rios; Ikenna Odinaka; Rajeev Kumar Dokania; Sasikanth Manipatruni
IPC分類
H03K19/23; H03K19/0185; G06F7/487; H03K19/017; G06F7/501; H03K19/17736
技術(shù)領(lǐng)域
reset,gate,majority,pull,capacitors,adder,minority,multiplier,gates,node
地域： CA CA San Francisco

摘要

A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

說明書

Example 7a: The apparatus of example 6a, wherein the reset mechanism comprises: a first pull-up device coupled to the AND gate such that the first pull-up device is connected to the second terminals of a first set of capacitors of the AND gate, wherein the first pull-up device is controllable by a first control; and a first pull-down device controllable by a second control, wherein the first pull-down device is coupled to the second terminals of the first set of capacitors of the AND gate.

Example 8a: The apparatus of example 7a, wherein the reset mechanism includes: a second pull-up device which is controllable by a third control, wherein the second pull-up device is coupled to the second terminals of a second set of capacitors of the 1-bit full adder; and a second pull-down device which is controllable by a fourth control, wherein the second pull-down device is coupled to the second terminals of the second set of capacitors of the 1-bit full adder.

Example 9a: The apparatus of example 8a, wherein the apparatus comprises: a third pull-up device which is controllable by a fifth control, wherein the third pull-up device is coupled to the second terminals of a third set of capacitors of the 1-bit full adder; and a second pull-down device which is controllable by a sixth control, wherein the second pull-down device is coupled the second terminals of the third set of capacitors of the 1-bit full adder.

Example 10a: The apparatus of example 1a, wherein the non-linear polar material includes ferroelectric material.

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