Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
Example 20a: The system of example 17a, wherein the non-linear polar material includes one of a ferroelectric material or paraelectric material.
Example 1b: An apparatus comprising: a CMOS based AND gate; a 1-bit full adder comprising a majority gate or a minority gate coupled to an output of the CMOS based AND gate, wherein the 1-bit full adder comprises non-linear polar material; and a reset mechanism comprising logic to condition first terminals of capacitors of the 1-bit full adder, the capacitors comprising the non-linear polar material, wherein the reset mechanism is to reset second terminals of the capacitors during a reset phase separate from an evaluation phase.
Example 2b: The apparatus of example 1b comprises: a first inverter which is coupled to a 3-input majority gate of the 1-bit full adder; and a first NOR gate coupled to an output of the first inverter, wherein the first NOR gate is controllable by a first reset, wherein an output of the first NOR gate is a carry output, wherein the first reset is to condition the output of the first NOR gate during the reset phase.
Example 3b: The apparatus of example 2b comprises a second inverter coupled to the output of the first NOR gate, wherein an output of the second inverter is coupled to a 5-input majority gate of the 1-bit full adder.
Example 4b: The apparatus of example 3b comprises: a third inverter coupled to the 5-input majority gate; and a second NOR gate coupled to an output of the third inverter, wherein the second NOR gate is controllable by the first reset, wherein the first reset is to condition the output of the second NOR gate during the reset phase, wherein the output of the second NOR gate is a sum output.
