Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
Example 9c: An apparatus comprising: an AND gate to receive a multiplier and a multiplicand; a 1-bit full adder comprising a majority gate or a minority gate directly connected to an output of the AND gate, wherein the 1-bit full adder comprises non-linear polar material, wherein the 1-bit full adder is to receive a sum input and a carry input; and a reset mechanism comprising logic to condition first terminals of a set of capacitors of the 1-bit full adder, the set of capacitors comprising the non-linear polar material, wherein the reset mechanism is to reset second terminals of the set of capacitors sequentially during a reset phase separate from an evaluation phase, wherein the reset mechanism is to apply a predetermined input to the multiplier, the multiplicand, the sum input, and the carry input during the reset phase.
Example 10c: The apparatus of example 9c, wherein the reset mechanism is to sequentially pull-up and pull-down the second terminals during the reset phase, and to allow the second terminals to float during the evaluation phase.
Example 11c: The apparatus of example 9c, wherein the non-linear polar material comprises ferroelectric material.
Example 12c: The apparatus of example 9c, wherein the set of capacitors comprises a first set of capacitors, wherein the reset mechanism comprises: a first pull-down device coupled to a 3-input majority gate such that the first pull-down device is connected to the second terminals of the first set of capacitors of the 3-input majority gate, wherein the first pull-down device is controllable by a first control; and a first pull-up device coupled to the 3-input majority gate such that the first pull-down device is connected to the second terminals of the first set of capacitors of the 3-input majority gate, wherein the first pull-down device is controllable by a second control.
