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Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism

專(zhuān)利號(hào)
US11888479B1
公開(kāi)日期
2024-01-30
申請(qǐng)人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Amrita Mathuriya; Rafael Rios; Ikenna Odinaka; Rajeev Kumar Dokania; Sasikanth Manipatruni
IPC分類(lèi)
H03K19/23; H03K19/0185; G06F7/487; H03K19/017; G06F7/501; H03K19/17736
技術(shù)領(lǐng)域
reset,gate,majority,pull,capacitors,adder,minority,multiplier,gates,node
地域： CA CA San Francisco

摘要

A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

說(shuō)明書(shū)

Example 13c: The apparatus of example 12c, wherein the set of capacitors includes a second set of capacitors, wherein the reset mechanism includes: a second pull-down device controllable by a third control, wherein the second pull-down device is coupled to a 5-input majority gate such that the second pull-down device is connected to the second terminals of the second set of capacitors of the 5-input majority gate; and a second pull-up device controllable by a fourth control, wherein the second pull-up device is coupled to the 5-input majority gate such that the second pull-up device is connected to the second terminals of the second set of capacitors of the 5-input majority gate.

Example 14c: The apparatus of example 13c, wherein the reset mechanism is to turn on and off the first pull-up device and the first pull-down device before the reset mechanism is to turn on and off the second pull-up device and the second pull-down device.

Example 15c: A system comprising: a processor circuitry to execute one or more instructions; a communication interface communicatively coupled to the processor circuitry; and a memory coupled to the processor circuitry, wherein the processor circuitry comprises a multiplier circuitry which includes: an AND gate comprising non-linear polar material; and a reset mechanism comprising logic to condition first terminals of a set of capacitors of the AND gate, the set of capacitors comprising non-linear polar material, wherein the reset mechanism is to reset second terminals of the set of capacitors sequentially during a reset phase separate from an evaluation phase.

Example 16c: The system of example 15c, wherein the multiplier circuitry: a 1-bit full adder comprising a majority gate or a minority gate directly connected to an output of the AND gate, wherein the 1-bit full adder comprises non-linear polar material.

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