Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
Example 17c: The system of example 16c, wherein the non-linear polar material includes ferroelectric material or paraelectric material.
Example 18c: The system of example 15c, wherein the reset mechanism is to sequentially pull-up and pull-down the second terminals during the reset phase, and to allow the second terminals to float during the evaluation phase.
Example 19c: The system of example 18c comprises: a first inverter which is coupled to a 3-input majority gate of 1-bit full adder; and a first NOR gate coupled to an output of the first inverter, wherein the first NOR gate is controllable by a first reset, wherein an output of the first NOR gate is a carry output, wherein the first reset is to condition the output of the first NOR gate during the reset phase, wherein an output of the first inverter is coupled to a 5-input majority gate of the 1-bit full adder.
Example 20c: The system of example 19c comprises: a second inverter coupled to the 5-input majority gate; and a second NOR gate coupled to an output of the second inverter, wherein the second NOR gate is controllable by the first reset, wherein the first reset is to condition the output of the second NOR gate during the reset phase, wherein the output of the second NOR gate is a sum output.
