Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
In some embodiments, when the non-linear polar material is a paraelectric material, all inputs to the multiplier cell are set to 0. The reset mechanism is simpler for a multiplier cell when the multiplier cell comprises capacitors with paraelectric material. In some embodiments, when the non-linear polar material is a paraelectric material, the reset mechanism comprises pull-down devices to pull-down the floating nodes during the reset phase. In some embodiments, when the inputs to the multiplier cell are set to 1 during the reset, the reset mechanisms pull-up the floating nodes during the reset phase. Once the reset phase is over (e.g., when the normal phase or evaluation phase begins), the reset mechanism is disabled. In various embodiments, the pull-up or pull-down events on the floating nodes depends on the conditioning of inputs of the paraelectric or ferroelectric based capacitors of the majority or minority gates.
There are many technical effects of the various embodiments. For example, extremely compact multiplier circuitry is formed using the design of various embodiments. The non-linear polar material used in the multiplier can be ferroelectric material, para-electric material, or non-linear dielectric. The majority gate, minority gate and/or threshold gate of various embodiments lowers the power consumption of the multiplier circuit because the majority gate, minority gate and/or threshold gate do not use switching transistors and the interconnect routings are much fewer than the interconnect routings used in transitional CMOS logic gates. For example, 10x less interconnect length is used by the majority gate and threshold gate of various embodiments than traditional CMOS circuits for the same function and performance. The capacitor with non-linear polar material provides non-volatility that allows for intermittent operation and zero power drain when not in use.
