Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說(shuō)明書
Example 5f: The apparatus of example 4f, wherein the NOR gate is a first NOR gate, wherein the logic comprises a second NOR gate, wherein the second NOR gate is coupled to an output of the first NOR gate, wherein the second NOR gate is controllable by the reset control, wherein an output of the second NOR gate is a carry out.
Example 6f: The apparatus of example 4f, wherein an output of the NOR gate is coupled to a 5-input majority gate of the 1-bit full adder.
Example 7f: The apparatus of example 6f comprises a buffer coupled to an output of the 5-input majority gate.
Example 8f: The apparatus of example 2f, wherein the reset mechanism comprises: a first pull-up device or a first pull-down device coupled to the AND gate such that the first pull-up device is connected to the second terminals of a first set of capacitors of the AND gate, wherein the first pull-up device or the first pull-down device is controllable by a first control.
Example 9f: The apparatus of example 1f, wherein the reset mechanism includes: a second pull-up device or a second pull-down device which is controllable by a second control, wherein the second pull-up device or the second pull-down device is coupled to the second terminals of a second set of capacitors of the 1-bit full adder.
Example 10f: The apparatus of example 1f, wherein the apparatus comprises: a third pull-up device or a third pull-down device which is controllable by a third control, wherein the third pull-up device or the third pull-down device is coupled to the second terminals of a third set of capacitors of the 1-bit full adder.
