Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
Example 11f: The apparatus of example 1f, wherein the paraelectric material includes one of: SrTiO3, Ba(x)Sr(y)TiO3 (where x is ?0.5, and y is 0.95)), HfZrO2, Hf—Si—O, La-substituted PbTiO3, and/or PMN-PT based relaxor ferroelectrics.
Example 12f: An apparatus comprising: a 1-bit full adder comprising a majority gate or a minority gate, wherein the 1-bit full adder comprises paraelectric material; and a reset mechanism comprising logic to condition first terminals of a set of capacitors of the 1-bit full adder, the set of capacitors comprising the paraelectric material, wherein the reset mechanism is to reset second terminals of the set of capacitors during a reset phase separate from an evaluation phase, wherein the logic comprises a transmission gate controllable by a reset control, wherein the transmission gate is coupled to the set of capacitors.
Example 13f: The apparatus of example 12f comprising: an AND gate coupled to the 1-bit full adder.
Example 14f: The apparatus of example 13f, wherein: the AND gate comprises a majority gate or a minority gate having the paraelectric material; the AND gate comprises paraelectric material; or the AND gate is a CMOS based AND gate.
Example 15f: The apparatus of example 12f, wherein the transmission gate is coupled to a pull-down device or a pull-up device which is to force a condition on some capacitors of a set of capacitors.
Example 16f: The apparatus of example 13f, wherein the reset mechanism comprises: a first pull-up device or a first pull-down device coupled to the AND gate such that the first pull-up device is connected to the second terminals of a first set of capacitors of the AND gate, wherein the first pull-up device or the first pull-down device is controllable by a first control.
