Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
Example 17f: The apparatus of example 12f, wherein the reset mechanism includes: a second pull-up device or a second pull-down device which is controllable by a second control, wherein the second pull-up device or the second pull-down device is coupled to the second terminals of a second set of capacitors of the 1-bit full adder.
Example 18f: The apparatus of example 12f, wherein the apparatus comprises: a third pull-up device or a third pull-down device which is controllable by a third control, wherein the third pull-up device or the third pull-down device is coupled to the second terminals of a third set of capacitors of the 1-bit full adder.
Example 19f: A system comprises: a memory to store one or more instructions; a processor circuitry coupled to the memory, wherein the processor circuitry is to execute the one or more instructions; and a communication interface to allow the processor circuitry to communicate with another device, wherein the processor circuitry includes: a 1-bit full adder comprising a majority gate or a minority gate, wherein the 1-bit full adder comprises paraelectric material; and a reset mechanism comprising logic to condition first terminals of a set of capacitors of the 1-bit full adder, the set of capacitors comprising the paraelectric material, wherein the reset mechanism is to reset second terminals of the set of capacitors during a reset phase separate from an evaluation phase, wherein the logic comprises one or more NOR gates controllable by a reset control.
Example 20f: The system of example 19f comprising: an AND gate coupled to the 1-bit full adder.
