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Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism

專(zhuān)利號(hào)
US11888479B1
公開(kāi)日期
2024-01-30
申請(qǐng)人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Amrita Mathuriya; Rafael Rios; Ikenna Odinaka; Rajeev Kumar Dokania; Sasikanth Manipatruni
IPC分類(lèi)
H03K19/23; H03K19/0185; G06F7/487; H03K19/017; G06F7/501; H03K19/17736
技術(shù)領(lǐng)域
reset,gate,majority,pull,capacitors,adder,minority,multiplier,gates,node
地域： CA CA San Francisco

摘要

A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

說(shuō)明書(shū)

Example 4g: The apparatus of example 1g, wherein the third terminal is coupled to a third set of capacitors, wherein an individual capacitor comprises the third paraelectric material, wherein the reset mechanism is to condition inputs to the third set of capacitors in the reset phase.

Example 5g: The apparatus of example 1g, wherein the reset mechanism is to pull-up or pull-down the first terminal to a supply level or to a ground, respectively.

Example 6g: The apparatus of example 5g, wherein the reset mechanism is to pull-up or pull-down the second terminal to the supply level or to the ground.

Example 7g: The apparatus of example 6g, wherein the reset mechanism is to pull-up or pull-down the third terminal to the supply level of the ground.

Example 8g: The apparatus of example 1g, wherein at least two inputs of the first logic, the second logic, and the third logic are conditioned to logic 1 or logic 0 by the reset mechanism during the reset phase.

Example 9g: The apparatus of example 1g, wherein the first paraelectric material, the second paraelectric material, and the third paraelectric material are same.

Example 10g: The apparatus of example 1g, wherein the first paraelectric material, the second paraelectric material, and the third paraelectric material are different.

Example 11g: The apparatus of example 1g, wherein the first paraelectric material, the second paraelectric material, or the third paraelectric material includes one of: SrTiO3, Ba(x)Sr(y)TiO3 (where x is ?0.5, and y is 0.95)), HfZrO2, Hf—Si—O, La-substituted PbTiO3, and/or PMN-PT based relaxor ferroelectrics.

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