The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.
FIG. 1 illustrates a set of plots showing behavior of a ferroelectric capacitor, a paraelectric capacitor, and a linear capacitor.
FIG. 2 illustrates a 3-input majority or minority gate with non-linear input capacitors, in accordance with some embodiments.
FIG. 3A illustrates a multiplier cell comprising a 1-bit full adder and an AND gate, wherein the multiplier cell comprises a reset mechanism, wherein at least one of the 1-bit full adder and/or the AND gate comprise ferroelectric or paraelectric material, in accordance with some embodiments.
FIG. 3B illustrates a multiplier cell having a 1-bit full adder and an AND gate using majority or minority gates with non-linear input capacitors (e.g., ferroelectric capacitor), in accordance with some embodiments.
FIG. 4 illustrates an N×N multiplier array, wherein each cell of the array includes a 1-bit full adder and an AND gate, wherein at least one of the 1-bit full adder and/or the AND gate comprise ferroelectric or paraelectric material, in accordance with some embodiments.
