FIG. 2 illustrates a 3-input majority gate 200 (or minority gate) with non-linear input capacitors, in accordance with some embodiments. In some embodiments, 3-input majority gate 200 comprises non-linear input capacitors C1n1, C2n1, and C3n1 that receives digital signals a, b, and c, respectively. Here, signal names and node names are interchangeably used. For example, ‘a(chǎn)’ refers to node ‘a(chǎn)’ or signal ‘a(chǎn)’ depending on the context of the sentence. One end or terminal of capacitor C1n1 is coupled to node a while the other end of capacitor C1n1 is coupled to summing node Vs. The same is true for other non-linear capacitors C2n1 and C3n1 as shown. In some embodiments, 3-input majority gate 200 comprises a driver circuitry 201. In this example, driver circuitry 201 is an inverter. In other embodiments, other types of driver circuitries can be used such as NAND gate, NOR gate, multiplexer, buffer, and other logic gates. The majority function is performed at summing node Vs as Majority (a, b, c). In this example, since driver circuitry 201 is an inverter, minority function is performed at output “out” as Minority (a, b, c).
