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Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism

專(zhuān)利號(hào)
US11888479B1
公開(kāi)日期
2024-01-30
申請(qǐng)人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Amrita Mathuriya; Rafael Rios; Ikenna Odinaka; Rajeev Kumar Dokania; Sasikanth Manipatruni
IPC分類(lèi)
H03K19/23; H03K19/0185; G06F7/487; H03K19/017; G06F7/501; H03K19/17736
技術(shù)領(lǐng)域
reset,gate,majority,pull,capacitors,adder,minority,multiplier,gates,node
地域： CA CA San Francisco

摘要

A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

說(shuō)明書(shū)

In some embodiments, AND gate 302 is a CMOS (or any other transistor technology) based AND gate (e.g., a NAND gate followed by an inverter). In some embodiments, AND gate 302 is a threshold gate. In some embodiments, AND gate 302 is a majority only gate. In some embodiments, AND gate is a hybrid gate which is a mix of majority gate and CMOS based devices. In some embodiments, the AND gate comprises two capacitors with non-linear polar material. These two capacitors are coupled to the inputs of the AND gate. For example, a first capacitor is coupled to a first input, while a second capacitor is coupled to a second input. The other terminals of the first capacitor and the second capacitor are coupled to a common node, which is a summation node or floating node. In the case where AND gate 302 has two capacitors, there may be no need to have a third capacitor in the AND gate with its input coupled to ground. AND gate 302 produces a partial multiplication result of multiplying X and Y, while adder 301 adds that partial multiplication result with a multiplication result Sum_in from a previous multiplier cell (not shown) to generate a full multiplication result as Sum_out. The Carry-out (Cout) of adder 301 becomes the Cin for the subsequent multiplier cell (not shown). Sum_out can be used as a result and/or as Sum_in for a subsequent multiplier cell. As such, an N×N multiplier is made using the basic multiplier cell 300 repeated N×N times and connected as discussed herein. In various embodiments, adder 301 and/or AND gate 302 include non-linear polar material.

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