Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
In various embodiments, multiplier cell 300 receives a Reset to preset (e.g., pre-discharge and/or pre-charge) the floating nodes in the majority or minority gates of the multiplier cell. The reset is part of a reset mechanism which is specific to the kind of non-linear capacitor material. The reset mechanism of various embodiments controls the voltage at the inputs (e.g., Sum_in, C_in_X, and/or Y) of the non-linear capacitors and the floating node (also referred to as the summation node) simultaneously. If AND gate 302 is a CMOS AND gate, then input Y may not be preconditioned during the reset phase. If AND gate 302 is a majority gate, then input Y is preset as described with reference to various embodiments. In some embodiments, the voltage across the non-linear capacitors is controlled on both terminals of the non-linear capacitors. In some embodiments, one terminal of the non-linear capacitors is applied to preset input signal with a desired or known voltage during reset. In some embodiments, the other terminal of the non-linear capacitors, which is connected to the floating node, is pull-up and/or pull-down in a sequence depending on the input voltage conditioning and/or type of non-linear polar material (e.g., ferroelectric vs. paraelectric). As such, deterministic voltages are established on both ends or terminals of the non-linear capacitors. By controlling the voltages at both ends or terminals of the capacitors and setting it accordingly to establish a majority function at the floating node, correct polarization state is established for the non-linear capacitors. As such, a charge balance is created on the floating node such that logic gates of the multiplier cell work as majority gates until a sufficient charge leaks out through various components needing a reset phase again. Here, a sufficient amount of charge is an amount of charge that when leaks out, the logic gate loses correct functionality and starts to produce incorrect results. In one example, the loss of this sufficient charge can take a up to a couple of microseconds to happen depending upon the leakage of the capacitors involved and the transistor components.
