Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
A particular charge balance may be needed to be maintained at the floating nodes a1, c1, and s1 to get the expected majority (or minority) function. However, over time, the charge on the floating nodes a1, c1, and s1 leaks away due to the leakage of the various components present in a system comprising the multiplier cell. Source of this leakage can be leakage from gates of a transistors of buffers 321, 322, and 324 and/r inverter 323 coupled to the floating nodes. The source of the leakage can also be from the capacitors themselves. In some embodiments, a reset mechanism is provided which reestablishes the charge balance on the floating nodes a1, c1, and s1 for correct functionality of the majority (or minority) functions. In some embodiments, when the capacitors of multiplier cell 320 are made from ferroelectric material, then input X is set to 0, input Y is set to 1, input Sum_in is set to 0, and input C_in is set to 0. The voltages on inputs X and Y can be flipped so long as one of the inputs is a zero and the other input is a logic 1. In various embodiments, the reset mechanism ensures that nodes indicated by identifier 325 are set to logic 1 during a reset phase. In various embodiments, during reset, nodes indicated by identifier 326 is expected to stay at logic 1 when c1 node is pulsed by pull-up and pull-down events on node c1. In various embodiments, the reset mechanism ensures that nodes indicated by identifier 327 are to be at logic 0 when floating nodes a1, c1, and s1 are pulsed. For example, when floating nodes a1, c1, and s1 are pulsed by pull-up and pull-down events on those nodes, then during reset phase nodes a2, Cout, and Sum_out are expected to by at logic 0.
