Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
1-bit full adder is provided for each column that sums a locally computed partial product (X Y), an input passed into the majority or minority gate multiplier cell from above (Sum In), and a carry Ci passed from a majority or minority gate multiplier cell diagonally above. It generates a carry-out (Cout or Co) and a new sum (Sum Out or So). N x N multiplier 400 shows the interconnection of 16 of these majority or minority gate multiplier cells to implement the full multiplier function. However, any number of majority or minority gate multiplier cells can be used. The input Ai values are distributed along cell diagonals and the input Bi values are passed along rows. This implementation uses the same gate count as the previous one: 16 AND gates and 12 adders. In various embodiments, the top row may not use adders. The outputs S0 though S6 of 1-bit adders 3010 through 3016 are the results of the bit-wise multiplication. In some embodiments, adders 3010 through 3012 (shown as dotted boxes) can be removed since they are simply adding zero to the input A. In one such example, the output of 3000 is S0 and the output of 30011 is S1. Various figures here describe the different implementations of multiplier cell 300 and 1-bit full adder 301 with their reset mechanism.
In various embodiments, each multiplier cell 300 and adder 301 receive reset signals (e.g., rl, rh, rlb, rhb, rst) to reset the floating nodes of the multiplier cell 300 and adder 301. Depending on the type of non-linear polar material (e.g., ferroelectric or paraelectric) for the capacitors of multiplier cell 300 and adder 301, different types of reset mechanisms can be used.
