FIG. 7B illustrates a 1-bit full adder with a reset mechanism having two NOR gates, wherein the 1-bit-full adder includes majority or minority gates with ferroelectric capacitors, in accordance with some embodiments.
FIG. 8A illustrates a multiplier cell having a 1-bit full adder using majority or minority gates with ferroelectric capacitors and with reset mechanism comprising NOR gates that are sequentially reset, in accordance with some embodiments.
FIG. 8B illustrates a timing diagram for pull-up and pull-down events on the summation node of the majority or minority gates.
FIG. 8C illustrates a 1-bit full adder with a reset mechanism having two NOR gates, wherein the 1-bit-full adder includes majority or minority gates with ferroelectric capacitors that are sequentially reset, in accordance with some embodiments.
FIG. 9 illustrates a high-level majority-gate implementation of a multiplier-cell that is reset in multiple cycles, in accordance with some embodiments.
FIG. 10 illustrates a majority-gate chain comprising ferroelectric capacitors, wherein the majority-gate chain is sequentially reset, in accordance with some embodiments.
FIG. 11 illustrates a minority-gate chain comprising ferroelectric capacitors, wherein the minority-gate chain is sequentially reset, in accordance with some embodiments.
