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Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism

專利號
US11888479B1
公開日期
2024-01-30
申請人
Kepler Computing Inc.（US CA San Francisco）
發(fā)明人
Amrita Mathuriya; Rafael Rios; Ikenna Odinaka; Rajeev Kumar Dokania; Sasikanth Manipatruni
IPC分類
H03K19/23; H03K19/0185; G06F7/487; H03K19/017; G06F7/501; H03K19/17736
技術領域
reset,gate,majority,pull,capacitors,adder,minority,multiplier,gates,node
地域： CA CA San Francisco

摘要

A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

說明書

FIG. 12 illustrates a mix of majority-gate and minority gate in a chain comprising ferroelectric capacitors, wherein the chain of gates is sequentially reset, in accordance with some embodiments.

FIG. 13 illustrates a paraelectric based multiplier cell, in accordance with some embodiments.

FIG. 14A illustrates a multiplier cell having a 1-bit full adder and an AND gate using majority or minority gates with paraelectric capacitors, wherein the multiplier cell includes a transmission-gate based reset mechanism, in accordance with some embodiments.

FIG. 14B illustrates a 1-bit full adder having paraelectric capacitors, wherein the 1-bit full adder has a reset mechanism that includes transmission-gate, in accordance with some embodiments.

FIG. 15A illustrates a multiplier cell having a 1-bit full adder and an AND gate using majority or minority gates with paraelectric capacitors, wherein the multiplier cell includes a NOR gate based reset mechanism, in accordance with some embodiments.

FIG. 15B illustrates a 1-bit full adder using majority or minority gates with paraelectric capacitors, wherein the 1-bit full adder cell includes a NOR gate based reset mechanism, in accordance with some embodiments.

權利要求

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