FIG. 16A illustrates a multiplier cell having a 1-bit full adder and an AND gate using majority or minority gates with paraelectric capacitors, wherein the AND gate is directly connected to the 1-bit full adder, wherein the multiplier cell includes a dual NOR gate based reset mechanism, in accordance with some embodiments.
FIG. 16B illustrates a 1-bit full adder using majority or minority gates with paraelectric capacitors, wherein the 1-bit full adder cell includes a NOR gate based reset mechanism, in accordance with some embodiments.
FIG. 17 illustrates a multiplier cell having a 1-bit full adder and an AND gate using majority or minority gates with paraelectric capacitors, wherein the AND gate is directly connected to the 1-bit full adder, wherein the multiplier cell includes a single NOR gate based reset mechanism, in accordance with some embodiments.
FIG. 18 illustrates a multiplier cell having a 1-bit full adder and an AND gate using majority or minority gates with paraelectric capacitors, wherein the AND gate is directly connected to the 1-bit full adder, wherein the 3-input majority gate is directly connected to the 5-input majority gate, wherein the multiplier cell includes a single NOR gate based reset mechanism, in accordance with some embodiments.
FIG. 19 illustrates a multiplier cell having a 1-bit full adder and an AND gate using majority or minority gates with paraelectric capacitors as showing in FIG. 18, but without output driving buffer, in accordance with some embodiments.
