FIG. 8C illustrates 1-bit full adder 830 with a reset mechanism having two NOR gates, wherein the 1-bit full adder includes majority or minority gates with ferroelectric capacitors that are sequentially reset, in accordance with some embodiments. 1-bit full adder 830 is derived from multiplier cell 800 after AND gate 302, pull-up device MP1, and pull-down device MN1 are removed. Inputs X, Y, and Sum_in are repurposed. For example, input Sum_in is removed, input Y is relabeled as ‘A’ and input B is relabeled as ‘B’. During reset phase, rst is asserted, and inputs A, B, and C_in are conditioned as 0, 1, and 0, respectively. Note, A, B, and Cin are symmetric and can be swapped with one another. In this example, input terminals of capacitors CFE4, CFE5, and CFE6 are conditioned to 0, 1, and 0, respectively while input terminals of capacitors CFE7, CFE8, CFE9, CFE10, and CFE11 are conditioned to 0, 0, 0, 1, and 1 respectively. Floating node c1 is then pulled up and then pulled down using rh2 and r12, respectively, in accordance with various embodiments. In some embodiments, floating node s1 is pulled up and then pulled down using rh3 and r13, respectively. In some embodiments, floating node s1 is pulled up and then pulled down after floating node c1 is being pulled up and pulled down. In this case, the floating nodes are reset in a sequence. During the reset phase the outputs Cout and Sum_out are forced to logical 0 outputs.
