Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
Multiplier cell 900 is one of 500, 600, or 800. The inputs ‘a(chǎn)’, ‘b’, and ‘c’ of gate 901 are inputs to the capacitors CFE1, CFE2, and CFE2, respectively, of 3-input majority gate 901. The inputs ‘a(chǎn)’, ‘b’, and ‘c’ of gate 902 are inputs to the capacitors CFE4, CFE5, and CFE6, respectively, of 3-input majority gate 902. The inputs ‘a(chǎn)’, ‘b’, ‘c’, ‘d’, and ‘e’ of gate 903 are inputs to the capacitors CFE7, CFE8, CFE9, CFE10, and CFE11, respectively. Input ‘a(chǎn)’ of majority gate 901 is coupled to multiplier input X, input ‘b’ of majority gate 901 is coupled to multiplicand Y, and input ‘c’ is coupled to ground. By coupling one of the inputs (here, ‘c’) to ground, majority gate 901 is configured as an AND gate. The output of this AND gate is outl which is input to input ‘a(chǎn)’ of majority gate 901 and input ‘c’ of majority gate 903. Input ‘b’ of majority gate 902 receives carry input Cin, which is also provided as input ‘d’ to majority gate 903. Input ‘c’ of majority gate 902 receives sum input Sin, which is also provided as input ‘e’ to majority gate 903. The output Cout of majority gate 902 is inverted by inverter 904 to generate Coutb. Coutb is also provided as input to inputs ‘a(chǎn)’ and ‘b’ of majority gate 903. The output of majority gate 902 is Sum.
In some embodiments, after reset is released (e.g., when reset ends), the evaluation phase may begin after 1 or 2 cycles to allow charges of various nodes to stabilize. In some embodiments, the reset process is a sequential process that is sequentially performed on majority gates 901, 902, and 903, and in two cycles.
