Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
In the second cycle, inputs a, b, and c of majority gate 901 are set to logical levels 1, 1, and 0, respectively. Thereafter, the floating node a1 of majority gate 901 is pull-up by the pull-up transistor Mp1 via rh1. In the second cycle, inputs a, b, and c of majority gate 902 are set to logical levels 1, 1, and 0, respectively. Thereafter, the floating node c1 of majority gate 902 is pulled up by the pull-up transistor Mp3 rh2. In the second cycle, inputs a, b, c, d, e, and f of majority gate 903 are set to logical levels 0, 0, 1, 1, and 0, respectively. Thereafter, the floating node s1 of majority gate 903 is pulled down by the pull-down transistor Mn5 via r13. In various embodiments, setting inputs and performing pull-up (and pull-down) of each floating node occurs in a sequence from majority gate 901, followed by gate 902, and then gate 903. After cycle 2, the evaluation phase begins. In some embodiments, evaluation phase occurs after cycle 3 to allow charges of the various nodes to settle.
