FIG. 10 illustrates majority-gate chain 1000 comprising ferroelectric capacitors, wherein the majority-gate chain is sequentially reset, in accordance with some embodiments. Chain 1000 comprises majority gate 1001 coupled to majority gate 1002, which in turn is coupled to majority gate 1003. The output of majority gate 1001 is coupled to input ‘a(chǎn)’ of majority gate 1002. The majority gates can be like the majority gate used for AND gate 302, and include the pull-up and pull-down transistors as discussed with reference to various embodiments. While the sequential reset scheme is illustrated for 3-input majority gates, the embodiments are applicable to any odd input majority gate chain. The output of majority gate 1002 is coupled to to input ‘a(chǎn)’ of majority gate 1003. In various embodiments, each majority gate receives its respective reset signal. For example, majority gate 1001 is reset by r11 and rh1, majority gate 1002 is reset by r12 and rh2, and majority gate 1003 is reset by r13 and rh3. In some embodiments, the non-linear polar material (e.g., ferroelectric material) for the majority gates 1001, 1002, and 1003 are the same. In some embodiments, the non-linear polar material (e.g., ferroelectric material) for the majority gates 1001, 1002, and 1003 are different. For example, majority gate 1001 may use Bismuth ferrite (BFO), with a doping material where in the doping material is one of Lanthanum, or elements from lanthanide series of periodic table, while majority gate 1002 may use relaxor ferroelectric.
