Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說(shuō)明書
To reset majority-gate chain 1000, inputs a, b, and c of majority gate 1003 are conditioned to C32=0, C22=1, and C21=0 logical states, respectively. In cycles 1 and 2, majority gate 1003 operates in normal mode because majority gate 1001 and majority gate 1002 are being reset in cycles 1 and 2. Thereafter, at cycle 3, pull-up device Mp5 is turned on by rh3, and then at cycle 4 pull-down device Mn5 is turned on by r13. Note, when pull-down device Mn5 is turned on, pull-up device Mp3 is turned off. At cycle 5 and onwards, rh3 and r13 are disabled (e.g., rh3=1 and rh3=0) and majority gate 1003 is allowed to operate in normal mode. As such, chain 1000 is reset. This reset may happen after 1 to 2 microseconds of evaluation phase, in accordance with some embodiments.
In various embodiments, in a chain of majority gates having ferroelectric capacitors (e.g., the arrangement shown in
