FIG. 11 illustrates minority-gate chain 1100 comprising ferroelectric capacitors, wherein the minority-gate chain is sequentially reset, in accordance with some embodiments. A minority gate is a majority gate followed by an inverter. Chain 1100 comprises majority gates 1101, 1102, 1103 and inverters 1104, 1105, and 1106 coupled to the outputs of majority gates 1101, 1102, 1103, respectively. Output C31 of majority gate 1101 is inverted by inverter 1104 to generate output C31b. Output C32 of majority gate 1102 is inverted by inverter 1105 to generate output C32b. Output C33 of majority gate 1103 is inverted by inverter 1106 to generate output C33b. In various embodiments, each minority gate receives its respective reset signal. For example, majority gate 1101 is reset by rh1 and r11, majority gate 1102 is reset by rh2 and r12, and majority gate 1103 is reset by rh3 and r13.
To reset minority-gate chain 1100, inputs a, b, and c of minority gate 1101 are conditioned to C3=0, C2=1, and C1=0 logical states, respectively. Thereafter, at cycle 1, pull-up device Mp1 is turned on by rh1, and then at cycle 2 pull-down device Mn1 is turned on by ill. Note, when pull-down device Mn1 is turned on, pull-up device Mp1 is turned off. At cycle 3, r11 and rh1 are disabled (e.g., rh1=1 and rh1=0) and majority gate 1101 is allowed to operate in normal mode.
