Non-linear polar material based low power multiplier with NOR and NAND gate based reset mechanism
摘要
說明書
In some embodiments, a transmission gate TG3 is coupled to node Cout and is controllable by rst and rstb. In some embodiments, Cout is generated by inverter 1423 which is coupled to buffer 322. TG3 is coupled to node Cout and Coutb, where Coutb is coupled to paraelectric capacitors CPE10 and CPE11. In some embodiments, during reset phase, inputs X, Y, Sum_in and C_in are conditioned to logic 0, and then floating nodes a1, c1, and s1 are pulled down to ground. In some embodiments, floating nodes a1, c1, and s1 are pulled down simultaneously. In some embodiments, floating nodes a1, c1, and s1 are pulled down sequentially, where node a1 is pulled down first, followed by node c1, and then node s1. During the reset phase (e.g., rst=1), Coutb is forced to ground via pull-down transistor Mn5. After the reset phase (e.g., when rst=0), the evaluation phase begins. In some embodiments, there may be a difference of 1, 2 or more cycles between a reset phase after the evaluation phase. In some embodiments, the paraelectric capacitors are replaced with linear capacitors. The same reset mechanism may apply for linear capacitors, in accordance with some embodiments.
While the embodiments that use paraelectric capacitors illustrate a pull-down transistor on the floating nodes, a pull-up transistor may also be added to the floating nodes to balance leakage or to recondition the floating nodes when the input to the capacitors is changed. For example, when the input sequence to X, Y, and Sum_in is modified to logic 1, then the pull-up transistor is used to reset the floating nodes by pull-up the floating nodes to Vdd (e.g., power supply level).
