FIG. 16B illustrates 1-bit full adder 1620 using majority or minority gates with paraelectric capacitors, wherein the 1-bit full adder cell includes a NOR gate based reset mechanism, in accordance with some embodiments. 1-bit full adder 1620 is derived from multiplier cell 1600 after AND gate 302, pull-up device Mp1, and pull-down device Mn1 are removed. Inputs X, Y, and Sum_in are repurposed. For example, input Sum_in is removed, input Y is relabeled as ‘A’ and input B is relabeled as ‘B’. During reset phase, rst is asserted, and inputs A, B, and C_in are conditioned as 0, 0, and 0, respectively. Note, A, B, and Cin are symmetric and can be swapped with one another. In this example, input terminals of capacitors CPE4, CPE5, and CPE6 are conditioned to 0, 0, and 0, respectively while input terminals of capacitors CPE7, CPE8, CPE9, CPE10, and CPE11 are conditioned to 0, 0, 0, 0, and 0 respectively. During reset, NOR gate 1601 conditions logic 0 on node c1b, and hence input of paraelectric capacitors CPE10 and CPE11. Floating node c1 is then pull-down by Mn3 via rst signal, in accordance with various embodiments. In some embodiments, floating node s1 is pulled down by Mn5 via rst at the same time (or substantially the same time) when floating node c1 is being pulled down. In some embodiments, during the reset phase, the outputs Cout and Sum_out are forced to logical 0 outputs. For example, NOR gate 1602 forces Cout to be 0 during the reset phase. After the reset phase is over, evaluation phase begins. In various embodiments, the evaluation phase begins after one or more cycles (or a 1 or more microseconds) to allow charges on both terminals of the paraelectric capacitors to settle or stabilize.
