High resolution phase correcting circuit and phase interpolating device
地域：
Suwon-si
摘要
A phase correcting circuit includes a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, a first fine tuning circuit, and a second fine tuning circuit. The first fine tuning circuit includes a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal, and the second fine tuning circuit includes a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.
說明書
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This application claims priority to Korean Patent Application No. 10-2021-0128915, filed Sep. 29, 2021, the disclosure of which is hereby incorporated herein by reference.
Embodiments of the present disclosure described herein relate to integrated circuit devices, and, more particularly, to integrated circuit memory devices with enhanced clock signal timing.
Semiconductor devices such as a processor and a memory operate in response to a toggle period of a clock signal. For example, a semiconductor device may parse a communication signal of another device in synchronization with a timing at which the clock signal toggles. When a phase difference is present between the clock signal and the communication signal, the phase difference may cause an error of a communication signal that is transmitted/received by the semiconductor device.
As an operating speed of the semiconductor device becomes higher, the toggle period of the clock signal may become shorter. With a decrease in the toggle period of the clock signal, there is an ongoing need to tune the phase of the clock signal(s) more finely.
Embodiments of the present disclosure provide a high resolution phase correcting circuit and a phase interpolating device capable of finely correcting a phase of a clock signal.
權(quán)利要求
What is claimed is:1. A phase correcting circuit, comprising:a delay circuit configured to receive an input clock signal and to delay the input clock signal as much as a first delay time to output an output clock signal to a 0-th node; a first fine tuning circuit including a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal; and a second fine tuning circuit including a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor; wherein, in response to the first control signal, the output clock signal is further delayed as much as a second delay time shorter than the first delay time; and wherein, in response to the second control signal, the output clock signal is advanced as much as a third delay time shorter than the first delay time; and wherein a magnitude of the third delay time is smaller than a magnitude of the second delay time. 2. The phase correcting circuit of claim 1 , wherein the delay circuit includes one or more inverters. 3. The phase correcting circuit of claim 1 ,wherein the first fine tuning circuit includes a first NAND gate, and the second fine tuning circuit includes a second NAND gate; wherein the first terminal corresponds to a first input terminal of the first NAND gate, the second terminal corresponds to a second input terminal of the first NAND gate, and the third terminal corresponds to a first output terminal of the first NAND gate; and wherein the fourth terminal corresponds to a third input terminal of the second NAND gate, the fifth terminal corresponds to a fourth input terminal of the second NAND gate, and the sixth terminal corresponds to a second output terminal of the second NAND gate. 4. The phase correcting circuit of claim 1 ,wherein the first fine tuning circuit includes a first amplifier, and the second fine tuning circuit includes a second amplifier; wherein the first terminal corresponds to a first input terminal of the first amplifier, the second terminal corresponds to a first power terminal of the first amplifier, and the third terminal corresponds to a first output terminal of the first amplifier; wherein the fourth terminal corresponds to a second input terminal of the second amplifier, the fifth terminal corresponds to a second power terminal of the second amplifier, and the sixth terminal corresponds to a second output terminal of the second amplifier; and wherein the first amplifier is configured to be turned on in response to activation of the first control signal, and the second amplifier is configured to be turned on in response to activation of the second control signal. 5. The phase correcting circuit of claim 4 , wherein a gain of each of the first amplifier and the second amplifier is negative. 6. The phase correcting circuit of claim 1 ,wherein the first fine tuning circuit includes a first variable gain amplifier, and the second fine tuning circuit includes a second variable gain amplifier; wherein the first terminal corresponds to a first input terminal of the first variable gain amplifier, the second terminal corresponds to a first gain-control terminal of the first variable gain amplifier, and the third terminal corresponds to a first output terminal of the first variable gain amplifier; and wherein the fourth terminal corresponds to a second input terminal of the second variable gain amplifier, the fifth terminal corresponds to a second gain-control terminal of the second variable gain amplifier, and the sixth terminal corresponds to a second output terminal of the second variable gain amplifier. 7. A phase correcting circuit, comprising:a delay circuit configured to receive an input clock signal and to delay the input clock signal as much as a first delay time to output an output clock signal to a 0-th node; a load capacitor; and one or more fine tuning circuits connected in series between the 0-th node and the load capacitor; wherein each of the one or more fine tuning circuits includes an input terminal, a control terminal, and an output terminal; wherein the input terminal is connected with the 0-th node or an output terminal of a previous fine tuning circuit, the control terminal receives a control signal, and the output terminal is connected with an input terminal of a next fine tuning circuit or the load capacitor; wherein, in response to the control signal, a phase of the output clock signal is tuned as much as a second delay time shorter than the first delay time; wherein each of the one or more fine tuning circuits includes an amplifier; and wherein the input terminal corresponds to an input terminal of the amplifier, the control terminal corresponds to a power terminal of the amplifier, and the output terminal corresponds to an output terminal of the amplifier. 8. The phase correcting circuit of claim 7 , wherein the delay circuit includes one or more inverters. 9. The phase correcting circuit of claim 7 , wherein the control signals, which are each input to respective ones of the fine tuning circuits through the second terminal, are different from each other. 10. The phase correcting circuit of claim 9 , wherein a magnitude of the phase of the output clock signal, which is to be tuned, varies in response to the different control signals. 11. The phase correcting circuit of claim 7 , wherein each of the one or more fine tuning circuits includes a NAND gate; and wherein the input terminal corresponds to a first input terminal of the NAND gate, the control terminal corresponds to a second input terminal of the NAND gate, and the output terminal corresponds to an output terminal of the NAND gate. 12. The phase correcting circuit of claim 7 , wherein a gain of the amplifier is negative. 13. The phase correcting circuit of claim 7 , wherein the amplifier is a variable gain amplifier. 14. A phase interpolating device, comprising:a decoder configured to generate a first control signal and a second control signal based on a phase difference of a clock signal and a reference signal; a phase shift unit including a plurality of phase correction circuits connected in series; and a phase select unit; wherein each of the plurality of phase correction circuits includes:a delay circuit configured to receive an input clock signal and to delay the input clock signal as much as a first delay time to output an output clock signal to an output node; a first fine tuning circuit including a first terminal connected with the output node, a second terminal receiving the first control signal, and a third terminal; and a second fine tuning circuit including a fourth terminal connected with the third terminal, a fifth terminal receiving the second control signal, and a sixth terminal connected with a load capacitor; wherein, in response to the first control signal, the output clock signal is further delayed as much as a second delay time shorter than the first delay time; wherein, in response to the second control signal, the output clock signal is advanced as much as a third delay time shorter than the first delay time; and wherein the phase select unit is configured to determine whether to select, as a corrected clock signal, an output clock signal output from the delay circuit of each of the plurality of phase correction circuits, based on the phase difference. 15. The phase interpolating device of claim 14 ,wherein the first fine tuning circuit includes a first NAND gate, and the second fine tuning circuit includes a second NAND gate; wherein the first terminal corresponds to a first input terminal of the first NAND gate, the second terminal corresponds to a second input terminal of the first NAND gate, and the third terminal corresponds to a first output terminal of the first NAND gate; and wherein the fourth terminal corresponds to a third input terminal of the second NAND gate, the fifth terminal corresponds to a fourth input terminal of the second NAND gate, and the sixth terminal corresponds to a second output terminal of the second NAND gate. 16. The phase interpolating device of claim 14 ,wherein the first fine tuning circuit includes a first amplifier, and the second fine tuning circuit includes a second amplifier; wherein the first terminal corresponds to a first input terminal of the first amplifier, the second terminal corresponds to a first power terminal of the first amplifier, and the third terminal corresponds to a first output terminal of the first amplifier; wherein the fourth terminal corresponds to a second input terminal of the second amplifier, the fifth terminal corresponds to a second power terminal of the second amplifier, and the sixth terminal corresponds to a second output terminal of the second amplifier; wherein the first amplifier is configured to be turned on in response to activation of the first control signal; and wherein the second amplifier is configured to be turned on in response to activation of the second control signal. 17. The phase interpolating device of claim 14 ,wherein the first fine tuning circuit includes a first variable gain amplifier, and the second fine tuning circuit includes a second variable gain amplifier; wherein the first terminal corresponds to a first input terminal of the first variable gain amplifier, the second terminal corresponds to a first gain-control terminal of the first variable gain amplifier, and the third terminal corresponds to a first output terminal of the first variable gain amplifier; and wherein the fourth terminal corresponds to a second input terminal of the second variable gain amplifier, the fifth terminal corresponds to a second gain-control terminal of the second variable gain amplifier, and the sixth terminal corresponds to a second output terminal of the second variable gain amplifier. 18. The phase interpolating device of claim 14 , wherein a magnitude of the third delay time is smaller than a magnitude of the second delay time.
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