Below, an embodiment in which the control signal CS is implemented with a digital signal will be described. However, the present disclosure is not limited thereto. The phase interpolating device 1000 that operates in response to various types of control signals may be provided. For example, referring to an embodiment to be described with reference to FIG. 12, the control signal CS may be implemented in a pulse width modulation (PWM) manner or an analog manner.

Next, the phase select unit 1200 may receive the clock signals CLK0 to CLKn (having different phases) from the phase shift unit 1100. The phase select unit 1200 may receive a phase select signal SS from the decoder DEC, and may select one of the clock signals CLK0 to CLKn in response to the phase select signal SS. For example, when the phase select signal SS does not indicate an additional phase delay, the phase select unit 1200 may select the 0-th clock signal CLK0 as the output clock signal CCLK. As in the above description, the phase select unit 1200 may select one of the clock signals CLK0 to CLKn of various phases as the clock signal CCLK in response to the value of the phase select signal SS, which may be a multi-bit digital signal. In an embodiment, the phase select signal SS may include information about a phase difference of the clock signal CLK and the reference signal RCLK. That is, the phase select signal SS may be a signal indicating a desired magnitude of phase correction to be applied to the clock signal CLK.