FIG. 6 illustrates a circuit diagram in which a phase correction circuit of FIG. 5A is implemented. Referring to FIGS. 5A and 6, a phase correction circuit 130 may include a delay circuit 131 and a fine tuning circuit 132. The delay circuit 131 may include a single inverter INV, which provides a 180° delay. The functions and the operations of the phase correction circuit 130, the delay circuit 131, and the fine tuning circuit 132 are similar to those of the phase correction circuit 1300, the delay circuit 1310, and the fine tuning circuit 1320 of FIG. 5A, and thus, additional description will be omitted to avoid redundancy.

The fine tuning circuit 132 may include a switch SW. The switch SW may be turned on or turned off in response to the control signal CS. For example, the switch SW may be implemented with a p-channel metal oxide semiconductor (PMOS) transistor or an n-channel metal oxide semiconductor (NMOS) transistor (or a parallel combination of a PMOS transistor and an NMOS transistor, as a transmission gate). In this case, the control signal CS may be input to a gate terminal of the PMOS transistor or the NMOS transistor.