According to an embodiment, a phase correcting circuit may include a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node. A first fine tuning circuit may be provided that includes a first terminal connected with the 0-th node, a second terminal configured to receive a first control signal, and a third terminal. A second fine tuning circuit may be provided that includes a fourth terminal connected with the third terminal, a fifth terminal configured to receive a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.

According to an embodiment, a phase correcting circuit may include: (i) a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, (ii) a load capacitor, and (iii) one or more fine tuning circuits connected in series between the 0-th node and the load capacitor. Each of the one or more fine tuning circuits may include an input terminal, a control terminal, and an output terminal. The input terminal may be connected with the 0-th node or an output terminal of a previous fine tuning circuit, the control terminal may receive a control signal, and the output terminal may be connected with an input terminal of a next fine tuning circuit or the load capacitor. In response to the control signal, a phase of the output clock signal may be tuned as much as a second delay time shorter than the first delay time.