FIG. 7 illustrates a circuit diagram in which a phase correction circuit of FIG. 5B is implemented, according to an embodiment of the present disclosure. Referring to FIGS. 5B and 7, a phase correction circuit 2300 may include a delay circuit 2310 and first and second fine tuning circuits 2320a and 2320b. The delay circuit 2310 may include an inverter INV. However, the present disclosure is not limited thereto. For example, the delay circuit 2310 may include one or more inverters INV or may include a buffer defined, for example, by a pair of serially-connected inverters.

The functions and the operations of the phase correction circuit 2300, the delay circuit 2310, and the first and second fine tuning circuits 2320a and 2320b are similar to those of the phase correction circuit 1300, the delay circuit 1310, and the first and second fine tuning circuit 1320a and 1320b of FIG. 5B, and thus, additional description will be omitted to avoid redundancy.

Below, an embodiment in which each of fine tuning circuits is implemented with a NAND gate will be described with reference to FIGS. 7 to 9. However, the present disclosure is not limited thereto. For example, the present disclosure may include embodiments in which the fine tuning circuits 2320a and 2320b are implemented with any other semiconductor components. Embodiments in which a logic circuit is implemented with various components will be described in detail with reference to FIGS. 11 and 12.