In response to that the second control signal CSb is activated, the second NAND gate NANDb may operate to be equivalent to a second equivalent inverter EIV2. In this case, based on the Miller effect, the second parasitic capacitance CPb may operate to be equivalent to a second input Miller capacitance CPb1 and a second output Miller capacitance CPb2.

In an embodiment, the second input Miller capacitance CPb1 may be greater than the second parasitic capacitance CPb. For example, the second equivalent inverter EIV2 may perform an operation similar to that of an amplifier whose gain is ?1. Accordingly, referring to Equation 1 above, because “A” is 1′, a magnitude of the second input Miller capacitance CPb1 may be about two times the magnitude of the second parasitic capacitance CPb.

In an embodiment, when the first control signal CSa is activated, a magnitude of an equivalent capacitance seen from the delay circuit 2310 to the 0-th node NO may be increased based on the Miller effect for the first parasitic capacitance CPa. For example, because the first input Miller capacitance CPa1 greater than the first parasitic capacitance CPa is equivalently connected with the 0-th node NO, a time constant (e.g., RC time constant) of a circuit may increase. Accordingly, when the first control signal CSa is activated, the phase of the output clock signal CLKout may be finely tuned.