The second amplifier AMPb may be turned on or turned off in response to the second control signal CSb. For example, when the second control signal CSb is at the high level, the second amplifier AMPb may operate as an amplifier whose gain is negative (e.g., is ?A2). In this case, based on the Miller effect, the phase of the output clock signal CLKout may be tuned based on the second amplifier parasitic capacitance CAb. The principle that the phase of the output clock signal CLKout is adjustably tuned in response to the second control signal CSb is similar to that described with reference to FIGS. 7 to 9, and thus, additional description will be omitted to avoid redundancy.

In an embodiment, a magnitude of the phase of the output clock signal CLKout, which is tuned when the second control signal CSb is activated, may be smaller than a magnitude of the phase of the output clock signal CLKout, which is tuned when the first control signal CSa is activated.

FIG. 12 is a circuit diagram in which a phase correction circuit of FIG. 5B is implemented, according to an embodiment of the present disclosure. Referring to FIGS. 5B and 12, a phase correction circuit 4300 may include a delay circuit 4310, a first fine tuning circuit 4320a, and a second fine tuning circuit 4320b. The delay circuit 4310 may include the inverter INV. However, the present disclosure is not limited thereto. The delay circuit 4310 may include one or more inverters INV or may include a buffer.